This invention relates to digital-to-analog (D/A) converters and, in particular, to a D/A converter of the charge redistribution type.
D/A converters of the charge redistribution type normally include an array of binary weighted capacitors which are selectively charged (or discharged) to represent the value of a digital signal. After selected capacitors of the array are charged, the charge stored on the selected capacitors is then redistributed among all the capacitors of the array to produce an analog voltage representative of the digital signal.
This is best explained with reference to the prior art circuit of FIG. 1 in which 6-bit digital data signals (D1 through D6) are converted into an analog voltage at an output line OL by means of 6 capacitors (C1 through C6) and 6 switching circuits (S1 through S6). The six capacitors C1 through C6 are binary weighted with the smallest capacitor (i.e., C1) having a value equal to one unit of capacitance (C) and the largest capacitor (i.e., C6) having a value equal to 32 units of capacitance (32C). D6, the most significant bit (MSB) of information, is applied to and stored on the largest capacitor (i.e., C6) and D1, the least significant bit (LSB) of information, is applied to and stored on the smallest capacitor (i.e., C1).
As shown in FIG. 1, one side (X) of each capacitor (C1 through C6) is connected to output line, OL. The output line (OL) is selectively coupled either to Vcc volts via a first metal oxide semiconductor (MOS) transistor switch PL or to ground potential via a second MOS transistor switch NL. The other side (Y) of each capacitor (Ci) is selectively connected either via an MOS transistor switch (PSi) to Vcc volts or via an MOS transistor switch (NSi) to ground potential. Thus two switching transistors are used at each Y side of each capacitor to set each capacitor to a desired condition.
After the digital information is applied to and stored on selected capacitors, all the capacitors are connected in parallel causing the charge stored on selected capacitors to be redistributed among all the capacitors to produce an analog voltage representative of the applied digital input signal.
The sequence of steps and time periods required to perform digital signal to voltage conversion with the circuit of FIG. 1 is as follows.
1. During a first initialization time period, all the capacitors (Ci) are discharged to set them to the same initial condition. This is accomplished, for example, by turning PL OFF and NL ON; and turning all the PSi transistors OFF and all the NSi transistors ON.
2. During a second, subsequent, data loading time period, each digital data signal (Di) is applied via complementary transistors PSi or NSi to the Y side of a Ci capacitor and a charge corresponding to each data signal is stored on a Ci capacitor. This is accomplished, for example, by: (a) turning PL ON and NL OFF whereby OL is held at Vcc volts; and (b) each capacitor (Ci) is either charged if the input serial bit, Di, is "high" or Vcc volts, since Di-high turns ON its NSi transistor and turns OFF its PSi transistor; or remains uncharged if Di is a "low" or "zero" volts, since Bi-low turns ON its transistor PSi, and turns OFF its transistor NSi.
3. During a third, subsequent, recombination or conversion time period, all the Ci capacitors are connected in parallel to produce an analog voltage which is representative of the value of the digital signal. This is accomplished, for example, by: (a) turning PL and NL OFF; and (b) turning all the NSi transistors ON and all the PSi transistors OFF.
4. During a fourth, subsequent, time period, the analog voltage produced across the capacitors is read out via a transfer gate transistor (TR) coupling the output line OL to an amplifier AMP1.
The digital-to-analog converter (DAC) circuit of FIG. 1 is well suited for many applications. However, a number of problems exist with the DAC circuit of FIG. 1 where it is desired and/or necessary to form a high density DAC system. In such a system, many capacitors have to be charged quickly during a data load cycle. This is problematic because having to charge the capacitors (Ci) directly and sequentially in a short period of time requires large transistors to handle the large instantaneous currents needed to charge the largest capacitors. On the other hand where small low conductivity transistors are employed, the charging time becomes long and may exceed the time constraints of the system.
Furthermore, a significant problem exists with the circuit of FIG. 1 where it is desired to build a high density DAC system employing transistors such as those made of amorphous silicon. These transistors are easy and inexpensive to fabricate and it is therefore desirable to use this type of transistor. This is particularly so where a display panel is formed making use of these types of transistors whereby the display and the control circuitry can be formed using similar technology. Unfortunately, these transistors have low mobility, low gain and high threshold voltages. In addition, these transistors are presently available only in one conductivity type (i.e., N-channel conductivity type). As a result of their low gain and low conductivity and their relatively high threshold voltages (e.g., VT ranges from 3 to 5 volts), these transistors when operated in the source-follower mode tend to respond very slowly. The slow source-follower mode response presents a problem which is very pronounced in the amorphous silicon technology. However, in general, this problem exists whenever transistors of only one conductivity are available; i.e., the transistors provide good switching action when operated in the common source mode and poor (slow) action when operated in the source follower mode.
Still further it is desirable and or necessary to reduce the time to perform the digital-to-analog conversion, particularly in high density systems where a multiplicity of conversions must be performed in a very limited time.
Still further, it is desirable to reduce the number of components such as the use of two transistors per Y side of each capacitor. Reducing the number of components increases the yield and reliability of the circuit and enables the circuit to be laid out such that the circuit can be built more easily on pitch with the column and row conductors of a display panel intended for use with the DAC system.
The problems discussed above and others, discussed below, are resolved in circuits and systems embodying the invention.